1. Field of the Invention
This invention relates to bistable electronic circuit elements. More particularly, the invention relates to an improved bistable multivibrator, or flip-flop, for use in computers and related digital systems. The improved flip-flop has a novel circuit architecture which precludes the occurrence of metastable states in the flip-flop.
2. Description of Background Art
Most computers and related digital electronic computational and control apparatus are based upon a binary number system, and therefore utilize binary logic elements. According to the rules of binary logic, elements of a digital computer may reside in only one of two possible states: a first, "high" or "logic one" state represented by a positive voltage, for example, and a second, "low" or "logic zero" state, represented by a different voltage. Typically, the logic zero state is represented by a smaller voltage, such as a zero or negative voltage.
Computers usually contain a large number of a few types of functional electronic building blocks known as logic gates. One such building block, known as an "AND" gate, outputs a logic one voltage level only if all of its input signal voltage levels are at logic one levels. An "OR" gate outputs a logic one voltage level at its output terminal if any of its input terminals is at a logic one level.
In addition to the logic gates described above, computers employ a large number of data storage or memory elements Storage elements are used to retain logic levels for relatively long periods of time. For example, bistable storage elements, i.e., storage elements having only two possible stable states, may be employed in the memory of a computer to hold a pattern of ones and zeros which are the binary number representation of a customer's name and address, or other such data.
Binary computers also employ a large number of bistable storage elements in their computational and control sections, in addition to those contained in the memory sections of the computer. Such bistable storage elements are generally used to retain logic levels for a relatively short period of time. Thus, a bistable storage element may be used to store a number representing an intermediate result of a sequence of computations. Bistable storage elements may also be used in the control functions of the computer, directing various operations to be performed based upon the memory of previous logic signal levels which are stored temporarily in one or more bistable storage elements.
One type of bistable logical building block, or functional module, used in large numbers in digital computers is a device referred to as a bistable multivibrator, bistable or flip-flop. Modern computers employ flip-flops comprised of circuit elements all residing as an integrated circuit on a single silicon chip. Silicon chips smaller than a fingernail may contain hundreds or even thousands of such flip-flops. Whatever the physical form taken by the flip-flop, it must perform essentially the same logic function. Specifically, the flip-flop must reside in either a logic zero or a logic one state, the particular state depending on the type of flip-flop and the type of signal logic level inputs previously presented to the flip-flop.
Some rudimentary flip-flops, referred to as asynchronous latches, are designed to change output state whenever a particular input terminal changes from a logic zero to a logic one level, or vice versa. Most flip-flops, however, are designed to operate synchronously. A synchronous flip-flop requires a clock signal for its operation. Usually, the clock signal is continuously applied to the clock input terminal of the flip-flop, and changes logic states of the flip-flop at regular, precisely determined time intervals, to a state corresponding to a logic level applied to a data input terminal of the flip-flop.
In a synchronous flip-flop, a one or zero logic input level is first applied to the data input terminal of the flip-flop, depending on whether it is desired to set the flip-flop to a one output level, or reset it to a zero output level. Then, when the clock signal at the clock input terminal makes a predetermined transition, or logic level change, the logic level at the data input terminal of the flip-flop is copied into the flip-flop; causing the flip-flop output terminal to change to a desired memory state, in synchronization with the clock signal level transition.
Clocked flip-flops of the type described above are all made up of circuit elements in which signals are propagated at finite velocities. Therefore, conventional flip-flops require data input signal levels to reside at a data input terminal a minimum time interval before the clock signal transition occurs. That minimum time interval is referred to as the setup time. Also, the data input signal must remain at the desired logic level for a minimum duration known as the hold time.
If either or both the setup or hold-time requirements for a particular clocked flip-flop of the conventional prior art-type are violated, the flip-flop may assume an undesirable state which is referred to as a metastable state. The metastable state is characterized by a signal level at an output terminal of the flip-flop pausing at an amplitude intermediate between the logic one and logic zero levels characteristic of a properly operating flip-flop, and then falling back to the previous logic level, rather than switching completely. Logic gates, flip-flops and other digital-system building blocks to which the output terminals of a flip-flop may connect, all require that the level of a signal on an input terminal of the device be above a first, "high" threshold voltage for that signal to be recognized as a logic one signal. Similarly, all such functional building blocks required that a signal at an input terminal be below a second "low" threshold voltage to be recognized as a logic zero level. Therefore, an intermediate signal amplitude level, between the high and low threshold voltages, at the output terminal of a flip-flop in a metastable state causes the output states of a functional building block whose input terminal is connected to the flip-flop to be unpredictable.
The failure of a metastable flip-flop to achieve a known logic state upon the active transition of the clock input signal can cause unacceptable errors in the operation of digital systems. In particular, the partial switching of the output level of a metastable flip-flop can produce an undesirable pulse of short duration called a "runt" pulse or "glitch", which may propagate partially or fully through downstream logic building blocks. Also, an indeterminate delay in the return of the output signal level of a metastable flip-flop to its original state can cause system errors.
Any of the results of a flip-flop entering a metastable state described above can cause severe operational problems in a digital system. Such problems usually result in failure of an operating computer program, requiring a full system reset and restart for the program to run correctly to its conclusion.
Problems resulting from metastable operation of flip-flops, referred to in the industry as "metastability," are most frequently encountered when data or control signals are generated asynchronously with respect to the internal clock of the computer or other digital system. Such asynchronous signals can be generated in a variety of sources external to the computer, such as auxiliary equipment referred to as "peripherals" and including printers, other computers, and other such devices.
A recognition of the metastability problem existing in prior art flip-flops has prompted a number of proposed solutions to the problem. Examples of the proposed solutions are contained in the following U.S. patents:
East, et al., U.S. Pat. No. 3,761,739, Sept. 25, 1973, Non-Metastable Asynchronous Latch: Describes an asynchronous latch employing a tunnel diode to prevent the latch from entering a metastable state.
Paschal, et al., U.S. Pat. No. 4,093,878, June 6, 1978, De-Glitchable Non-Metastable Flip-Flop Circuit. Discloses a flip-flop which incorporates a Schmitt trigger as a thresholding device, and a resistor capacitor integrator circuit for the purpose of preventing the flip-flop from producing glitches or entering a metastable state.
DeRienzo, U.S. Pat. No. 4,282,489, Aug. 4, 1981, Metastable Detector. Discloses a detector circuit employing a substantial number of active logic building blocks and passive integrator elements for monitoring the complementary outputs of an operating flip-flop, and producing a signal indicating when those outputs have reached a defined stable state.
Leslie, U.S. Pat. No. 4,575,644, Mar. 11, 1986, Circuit For Prevention Of The Metastable State In Flip Flops. Discloses a "synchronizing" circuit for use with a clocked flip-flop having an asynchronous input signal. The circuit is reported to reduce the duration of, or inhibit, the metastable condition of an output terminal of the flip-flop by injecting an oscillator signal of higher frequency into the complementary output terminal of the flip-flop.
Campbell, U.S. Pat. No. 4,591,737, May 22, 1986, Master-Slave Multivibrator With Improved Metastable Response Characteristic. Discloses a master-slave flip-flop device in which the master flip-flop employs an extra driver transistor in each of the two logic gates comprising the master latch, for isolating function and load outputs of the gates, for the intended purpose of minimizing the duration of the undesirable metastable state of the master segment, thereby enhancing the propagation speed in which a stable state is established.
Whitely, U.S. Pat. No. 4,622,475, Nov. 11, 1986, Data Storage Element Having Input And Output Ports Isolated From Regenerative Circuit. Discloses a data storage element having input and output ports isolated from a regenerative latch portion so that the data transmission path is not through the latch. The stated purpose of the circuit arrangement is to "greatly reduce the probability of metastable occurrence."
The present invention was conceived of in response to a perceived need for a clocked bistable logic element or flip-flop in which the output signals are totally free of any metastable state, regardless of the data input signal pulse polarity, duration, or time relationship to the clock signal.